Circuit for processing reflected signals

ABSTRACT

A circuit for processing reflected signals is described. The reflected signal is delayed for a period of time which is equal to the period of the first half cycle of the reflected signal. It is also attenuated by an amount equal to the difference in amplitude between the first and second half cycles of the reflected signal. The delayed and attenuated signal is then combined with the reflected signal so that only the first half cycle of the reflected signal and the last half cycle of delayed signal remain.

United States Patent Langley [4 1 Mar. 21, 1972 [54] CIRCUIT FORPROCESSING 2,987,683 6/1961 Powers ..333/70 T REFLECTED SIGNALS3,315,171 1 4/1967 Becker ...333/70 T 3,482,190 12/1969 Brenin ..333/29[72] Inventor: Lawrence W. Langley, Sevema Park, Md.

73 A i nee: S mbionics Into M A Primary ExaminerHerman KarlSaalbach 1 8y mo" nnapo ls Assistant Examiner-Saxfield Chatmon, Jr, [22 Fil d: Mflr-970 Attorney-Birch, Swindler, McKie & Beckett 21 Appl. No.: 15,583ABSTRACT A circuit for processing reflected signals is described. The

[52] [1.8. CI. ..333/70 T, 333/29, reflected Signal is delayed for apriod of time which is equal [51] Int Cl "03h 7/10 03h 9/00 03k 5/159 tothe period of the first half cycle of the reflected signal. It is [58]Field 333/ 70T 29 76" 328/14 2 also attenuated by an amount equal to thedifference in am- 328/28 i 31 plitude between the first and second halfcycles of the reflected signal. The delayed and attenuated signal isthen combined with the reflected signal so that only the first half [56]Reerences cued cycle of the reflected signal and the last half cycle ofdelayed UNITED STATES PATENTS Signal remain- 2,922,965 1/1960 Harrison..333/70 T X 6 Claims, 8 Drawing Figures 25 26 2 21 (la) e DELAYATTENUATOR 28 29 SUM MING CIRCUIT so a PAIENIEIIMIIRZI I972 HGZI) I cIATTENUATOR DELAY IIuI SUMMING CIRCUIT INVENTOR W. LANGLEY v LAWRENCE 8M,3M, L44,-

ATTORNEYS CIRCUIT FOR PROCESSING REFLECTED SIGNALS BACKGROUND OF THEINVENTION The invention is directed to a circuit for processing dampedsinusodial signals. Although the manner in which the damped sinusodialsignal is generated is immaterial to the invention a more completeappreciation of the invention is obtained by presenting a few methods bywhich such signals can be generated.

The first method is the actual transmission of a damped sinusodialsignal. If a transducer, such as a piezo electric crystal is energizedby a short pulse of energy, for example, a high frequency electricalpulse, the output is an exponentially decaying ascoustical signal. Sucha signal is illustrated in FIG. Ia.

The damped signal can also be the result of damping caused by thereflecting medium. When an undamped short pulse of sinusodially varyingenergy is reflected, it is quite possible that the reflecting mediumwill dampen the transmitted signal and it will then appear asillustrated in FIG. 1a.

It is also possible that the receiving transducer will dampen thesignal. This will occur even if the transmitted pulse arrives at thereceiver without previous damping or distortion. FIG. Ia again isillustrative of the damped signal.

Irrespective of the manner in which the signal becomes damped thecharacteristics are much the same. The period remains constant dependingupon the characteristics of the damping medium or element. Also, theamplitude decay is exponential, and is determined by the characteristicsof the damping element.

In many types of equipment the operation is dependent upon thereproduction of the pulse from the damped reflected signal. Because manyof the characteristics of the initial pulse can be reproduced from thefirst one-half cycle of the damped reflected signal many attempts havebeen made to reproduce a facisimile of this portion of damped pulse.

Various systems have been devised for reproducing the first one-halfcycle of reflected signals and FIG. 2 is useful in illustrating anddescribing one well known technique. In the method illustrated in FIG. 2the actual first half cycle is not recovered. Instead an attempt is madeto produce as accurate a facsimile as possible of the first one-halfcycle.

FIG. 20 represents an exponentially decaying reflected signal. It isnoted that each of the successive one-half cycles is smaller in absoluteamplitude than the preceding half cycle. In order to reproduce afacsimile of the first one-half cycle 11 the entire reflected signal isintegrated. The integration results in a signal which represents theenvelope of damped signal as shown in FIG. 2b. The integrated pulse isthen differentiated resulting in a pulse 14 as shown in FIG. 2e. Thepulse 14 can be argued to be a facsimile of the first half cycle 11 ofFIG. 24 because the rise and fall of the pulse 14 are dependent upon therise and fall of the first half cycle. The time period of the first halfcycle 11 and the pulse 14 are therefore substantially equal.

Another well known method of reproducing the first half cycle 11 of areceived pulse is illustrated in FIG. 3. This method consists of greatlydamping the receiving mechanism so that only a highly attenuated firsthalf cycle and the more highly attenuated second and third half cyclesare transmitted through the receiving element. Consequently, thereflected pulse 15 includes the first half cycle 16 of relatively highamplitude but which is lower in amplitude than it would be in theabsence of the damping. The next two succeeding half cycles 17 and 18are more highly damped and for practical purposes the third half cycle18 is negligible. The decrease in amplitude of the first half cycle isundesirable for usages where the amplitude is an importantcharacteristic of the reflected signal.

SUMMARY OF THE INVENTION Although the two systems of reproducing afacsimile of the first half cycle of a reflected signal as illustratedby use of FIG. 2 and 3 have some utility they both suffer certaininherent disadvantages.

The two methods produce merely a facsimile of the first half cycle ofthe reflected signal. For this reason various spikes and othervariations of the first half cycle are lost. In this regard, it shouldbe noted that the wave form shown in FIG. 1a is idealized and an actualwave form would have spikes and distortions. The loss of thesecharacteristics in systems which produce merely a facsimile results inthe inability to accurately reproduce the sinusodial signal from whichthe damped signal were generated.

Furthermore, the method utilizing integration and differentiationrequires additional operational circuitry andaccordingly is expensiveand complex.

I The invention is accordingly directed to a system for actuallyrecovering the first one half cycle of the reflected signal rather thanreproducing a facsimile thereof.

In accordance with the invention, the received reflected signal isdelayed by a time period which is equal to the time between the zerocrossings of the first one half cycle. The output of the delay circuitis attenuated by an amount which is equal to the difference in theamplitudes of the first and second half cycles of the reflected signal.The output of the attenuator is then algebratically combined with thereflected signal so that the second and all succeeding half cycles ofthe reflected signal are cancelled while the first half cycle remainssubstantially unchanged and undistorted.

The proper usage of the system, therefore, requires an accurateknowledge of the time period of the first half cycle. This is easilyobtained because the wave form of the reflected signal is highlydependent upon the characteristics of the transducer used to receive thereflected signal. For example, assuming that the receiving transducer isa piezo crystal, it is easy to measure the characteristics of the piezocrystal and the characteristics of the received signal to thereby obtainthe time period of the first half cycle and the amplitudes of thesucceeding half cycles. For example, for an ultrasonic signal the pulsewidth of the first half cycle would be approximately 0.2 micro secondsand the difierence in amplitude of the first and second half cycleswould be one to two db. Equipped with this knowledge, it is an easymatter to build a delay circuit having a 0.2 micro second delay and anattenuator having a l to 2 db. attenuation.

BRIEF DESCRIPTION OF THE DRAWINGS DETAILED DESCRIPTION OF THE INVENTIONReferring to FIG. la the reflected pulse is indicated generally byreference numeral 19. The first one half cycle 20 I has a periodindicated by I. That is t represents the time required for the pulse torise from zero through its peak value and return to zero. The amplitudeof the first half cycle 20 is indicated by al while the amplitude of thesecond half cycle 21 is indicated by a2. As used herein the amplitudesa1 and a2 are absolute values without regard to their positive ornegative polarities. The succeeding half cycles 22, 23, etc., are seento decay exponentially from the absolute values of the first and secondhalf cycles 20 and 21 respectively.

The primary purpose of the inventive circuit is the elimination of thehalf cycles 21, 22, 23, etc., while maintaining the first half cycle 20substantially undistorted, unattenuated and otherwise unchanged from itsreceived characteristics.

The first step in this is accomplished by delaying the entire reflectedsignal 19 by time period t as illustrated in FIG. lb. By simultaneouslyviewing FIGS. 1a and 1b it is noted that the first half cycle 20 of FIG.1b is now coincident in time with the second half cycle 21 of FIG. la.However, because their polarities are opposite the algebratic additionof these two pulses will result in a small pulse equal to the differencebetween the two initial pulses. That is, a pulse of amplitude equal toal-a2 and having a positive polarity. The polarity obviously woulddepend upon the actual reflected wave. However, it is positive for thewave 19 shown in the drawings. This difference is easily eliminated byattenuating the reflected signal by an amount equal to the differencebetween the two initial amplitudes. When the reflected signal 19 issubjected to the attenuation the first half cycle 20 of FIG. 1b is nowequal in absolute value or amplitude to the second half cycle 21 of FIG.la. Consequently, the algebraic addition of the unprocessed reflectedwave 19 and the attenuated and delayed reflected wave 19' will result inthe wave form shown in FIG. 1c. In this figure the first half cycle 20of the reflected wave 19 of FIG. remains substantially undistorted andunchanged. The last half cycle 24 of the delayed and attenuated signal19 will appear as a small negative pulse 24 in the wave form of FIG. 1c.However, this signal is insignificant as compared to the amplitude ofthe first half cycle 20. Furthermore, if necessary it can be removed byan inexpensive diode. This is especially convenient because its polarityis different from that of the first half cycle.

A few other negative and positive spikes will also appear across thewave form of FIG. 10. These will result from the linear attenuation ofthe reflected wave in the attenuating circuit. The entire reflectedsignal 19 is attenuated by an equal amount. However, the amplitude decayof the reflected signal is exponential. Consequentially, a slightinaccuracy will occur in the third and succeeding half cycles. However,the small pulses resulting from this inaccuracy will be of insignificantmagnitude and will have no affect on the control circuit. Furthermore,even if they are slightly higher than what is ordinarily considered tobe acceptable, an inexpensive filtering circuit can be used to removethem completely.

A few other spikes may also be present because the spikes and variationsof the first half cycle will differ from those of the second half cycle.There can also be filtered off by the same inexpensive filter used toremove the previously mentioned spikes.

FIG. 4 illustrates a preferred embodiment of the inventive circuit inwhich the processing circuitry is represented generally by referencenumeral 25. The processing circuit includes a delay circuit 26 which isused to delay the reflected signal by the amount equal to the time t ofFIG. 1a. The output of delay circuit 26 is injected into an attenuator27 which attenuates the reflected signal an amount equal to thedifference between the amplitudes al and a2 of FIG. la.

The input signal to the control circuit 25 which appears on the inputterminal 28 will be the damped signal 19 illustrated in FIG. la. Theoutput of the attenuator will appear as wave 19 shown in FIG. lb. Thewave form 19 of FIG. lb is injected into the summing circuit 29, as isthe initial damped signal 19 by way of line 30. The output of summingcircuit 29 is, therefore, the wave form shown in FIG. 1c. The output ofthe processing circuit 25 is composed almost solely of the initialone-half cycle 20 of the reflected signal. Although there are notillustrated any spikes or variations present on the first half cyclewhen it is first injected into the processing circuit such, will also bepresent on the output pulse because the first half cycle has not beenoperated upon or changed in any way. A very accurate reproduction of thesignal from which the damped signal was derived is therefore possible.

I claim:

1. A circuit for processing a signal to produce an output which is asubstantially unchanged portion of said signal comprising:

an input terminal for receiving said signal delay means for delayingsaid received signal by a time period which is less than the total timeperiod of said signal;

attenuation means for attenuating said delayed signal by a predeterminedamount;

summation means for algebraically summing said received signal and theoutput of said attenuation means so that the output of said processingcircuit presents a pulse which is substantially identical to a firstportion of said received signal.

2. The circuit of claim 1 wherein said first portion is the firstone-half cycle of said received signal.

3. The circuit of claim 1 wherein said predetermined amount is equal tothe difference in amplitude of the first onehalf cycle and the secondone-half cycle of said received signal.

4. The circuit of claim 1 wherein said delay period is the time periodof the first one-half cycle of said received signal.

5. The circuit of claim 2 wherein said predetermined amount ofattenuation is equal to the increment of amplitude decay naturallysuffered by said received signal between its first and second one-halfcycles;

and wherein said delay period is equal to the time period of said firstone-half cycle of said received signal.

6. The circuit of claim 1 wherein the first and second onehalf cycles ofsaid received signal are of opposite polarity;

said delay means delays said received signal by a time equal to the timeperiod of said first one-half cycle;

said attenuation means attenuates said first one-half cycle by an amountrequired to make its amplitude equal to the amplitude of said secondone-half cycle;

said summation means algebraically adds said received signal and outputof said attenuation means so that the preceding one-half cycle of thedelayed and attenuated signal cancels the succeeding one-half cycle ofthe received signal.

1. A circuit for processing a signal to produce an output which is a substantially unchanged portion of said signal comprising: an input terminal for receiving said signal; delay means for delaying said received signal by a time period which is less than the total time period of said signal; attenuation means for attenuating said delayed signal by a predetermined amount; summation means for algebraically summing said received signal and the output of said attenuation means so that the output of said processing circuit presents a pulse which is substantially identical to a first portion of said received signal.
 2. The circuit of claim 1 wherein said first portion is the first one-half cycle of said received signal.
 3. The circuit of claim 1 wherein said predetermined amount is equal to the difference in amplitude of the first one-half cycle and the second one-half cycle of said received signal.
 4. The circuit of claim 1 wherein said delay period is the time period of the first one-half cycle of said received signal.
 5. The circuit of claim 2 wherein said predetermined amount of attenuation is equal to the increment of amplitude decay naturally suffered by said received signal between its first and second one-half cycles; and wherein said delay period is equal to the time period of said first one-half cycle of said received signal.
 6. The circuit of claim 1 wherein the first and second one-half cycles of said received signal are of opposite polarity; said delay means delays said received signal by a time equal to the time period of said first one-half cycle; said attenuation means attenuates said first one-half cycle by an amount required to make its amplitude equal to the amplitude of said second one-half cycle; said summation means algebraically adds said received signal and output of said attenuation means so that the preceding one-half cycle of the delayed and attenuated signal cancels the succeeding one-half cycle of the received signal. 